The present invention relates generally to an exposure apparatus, and more particularly to an exposure apparatus and method used to manufacture various devices including semiconductor chips, a display device, a sensing device such as a magnetic head, an image pickup device such as a CCD, and a fine pattern for micromechanics. The present invention is suitable, for example, for a maskless exposure apparatus that utilizes a spatial modulation element, such as a micro-mirror array, and dispenses with a mask as an original.
Due to the demand by the large personal computer (“PC”) market, the fine processing of the semiconductor integrated circuits (“ICs”) has rapidly developed, and the design rule of 90 nm has been achieved. Many devices are produced as highly versatile and marketable microprocessor units (“MPUs”) and memories for use with the PCs. These MPUs and the memories use the same devices even for different PC manufacturers and models, and the same semiconductor devices are manufactured in huge quantities.
The information appliances are expected to be the largest market in the future for the semiconductor devices along with the widespread digital TVs, versatile cellular phones, networks, etc. The information appliances use unique semiconductor devices (or system LSIs) suitable for their manufacturers and models, and require the manufacture of various types of devices. The information appliances are designed and produced based on consumers' demands. Various consumers' demands require the manufacture of various products, and limit the number of units produced per model. Individual demands are so fluid that the products need to be put onto the market at the proper times based on the consumers' demands.
For the conventional semiconductor devices typified by the MPUs and memories, the same model can be produced in large quantities over a long time period of time. On the other hand, for the semiconductor devices (or system LSIs) in the information appliances, various types should be produced in small quantities only for short periods of time and placed in the market at the proper times.
A projection exposure apparatus, which has conventionally been used, projects a circuit pattern of a mask (or a reticle) onto a wafer etc. via a projection optical system and transfers the circuit pattern in a lithography that serves as the important technology for production of the semiconductor devices. For the fine processing and the high integration of the semiconductor devices, the projection exposure apparatus can now transfer a pattern smaller than the exposure wavelength by using, for example, a phase shift mask, etc. The phase shift mask is more complicated and thus more expensive than a conventional binary mask.
If the duplicate device is produced in large quantities, the mask cost per device is reduced. However, when the number of produced system LSIs are low, a mask cost increases, which makes the device and mask expensive, such as the phase shift mask. The information appliances are subject to keen price competition similar to conventional home electric appliances, and preferably avoid use of expensive semiconductor devices.
Accordingly, use of a direct imaging type of exposure apparatus (referred to as a “maskless exposure apparatus” hereinafter) to produce the system LSIs attracts attention. The maskless exposure apparatus uses no mask, and can start producing the devices without producing a mask once a device circuit design is determined. The maskless exposure apparatus eliminates the mask cost, and reduces the device producing time period.
For example, a maskless exposure apparatus that uses a similar light source to that of a conventional exposure apparatus is disclosed in U.S. Pat. No. 5,330,878. This maskless exposure apparatus arranges, as shown in FIG. 13, a micro-mirror array or spatial modulation element 1010 that includes many micro mirrors in place corresponding to a mask in the conventional exposure apparatus or between an illumination apparatus 1020 and a projection optical system 1030. The micro-mirror array 1010 generates a circuit pattern and dispenses with a mask. More specifically, the micro-mirror array 1010 generates a circuit pattern by controlling driving of thousands of micro mirrors each having a size of about 10 μm (and by controlling the light reflections through each micro mirror's inclination). The projection optical system 1030 projects and transfers a reduced size of the circuit pattern onto the wafer 1040. Here, FIG. 13 is a schematic sectional view of a structure of the conventional maskless exposure apparatus.
When the maskless exposure apparatus uses, as one pixel, each micro mirror in the micro-mirror array to form a pattern, and binary-controls its darkness and brightness, a pattern forming position is determined by the arrangement of the micro mirrors. For example, when the mirrors are arranged at a pitch of 10 μm and projected at a reduction of 1/100, the projected pattern forming position has a pitch of 100 nm. On the other hand, the current system LSI's minimum critical dimension (“CD”) is smaller than 100 nm, and the arrangement position has a pitch or grid of about 1 nm.
The micro-mirror array can mount about ten million micro mirrors each having a size of 10 μm at most. In the micro-mirror array that has ten million micro mirrors by arranging 2,500 micro mirrors longitudinally and 4,000 micro mirrors laterally, where each micro mirror has a size of 10 μm, a 1/10,000 reduction optical system should be used to project a pattern for a grid size of 1 nm. Since the entire micro-mirror array has a size of 25 mm×40 mm, the projected pattern size or angle of view is merely 2.5 μm×4 μm. The 1/10,000 reduction optical system is less feasible, and it takes an enormous time to connect patterns on the overall surface of a semiconductor wafer having a diameter of 300 mm for mass production.
One proposed technology to realize a virtual grid smaller than the mirror or pixel size used for actual patterning is the gray scale that varies the intensity of each pixel (or integral intensity) and forms a pattern image between pixels in the middle of grid.
The gray scale method is disclosed in International Application, Domestic Publication No. 2002-506233, U.S. Pat. No. 5,691,541, and Japanese Patent Application, Publication No. 2003-243300. International Application, Domestic Publication No. 2002-506233 proposes a method that slightly changes a reflecting angle of each micro mirror in the micro mirror array and varies the reflected light intensity. U.S. Pat. No. 5,691,541 proposes a method that divides the exposure into plural times, controls each pixel for each exposure and adjusts the integral exposure dose of a pixel. Japanese Patent Application, Publication No. 2003-243300 proposes a method that synthesizes and transfers images of plural spatial modulation elements that have adjusted different intensities.
However, the gray scale technology disclosed in International Application, Domestic Publication No. 2002-506233 needs an analog-to-digital conversion for each of a million of micro mirrors, and calibrates each micro mirror, causing a very complex and large system.
The gray scale technology disclosed in U.S. Pat. No. 5,691,541 requires multiple exposures for the improved intensity resolution, remarkably lowering the throughput.
The gray scale technology disclosed in Japanese Patent Application, Publication No. 2003-243300 complicates an optical system that synthesizes images formed by the distant spatial modulation elements, and has difficulties in assembly and adjustment.
The maskless exposure apparatus that uses the spatial modulation element should achieve a high throughput. For this purpose, it is conceivable to increase the number of pixels in the spatial modulation element and to extend an exposable area per unit time by enlarging an area for a single exposure and by shortening an exposure period. Any method requires a speed moving from one shot to another shot, which speed is generally referred to as a wafer stage speed. However, the current wafer stage speed has already reached the upper limit, and the improved throughput using the improved wafer stage speed cannot be expected.